The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 1997
Filed:
Mar. 13, 1995
Applicant:
Inventors:
Daisuke Kato, Poughkeepsie, NY (US);
Yohji Watanabe, Fishkill, NY (US);
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 63 ; 365 51 ; 365205 ;
Abstract
A layout arrangement for a semiconductor memory device provides additional space for locating an additional circuit device in a pitch limited circuit. A space or vacated area is created by laying out a circuit element in a manner in which the pitch of the circuit element and an adjacent circuit element is less than the pitch of two times the pitch of a connecting wire pair in a double-sided layout or less than the pitch of one connecting wire pair.
Kato, Daisuke. (1997). Irregular pitch layout for a semiconductor memory device (U.S. Patent No. 5636158). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5636158
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile