The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 1997
Filed:
May. 24, 1995
Semyon Sherstinsky, San Francisco, CA (US);
Shamouil Shamouilian, San Jose, CA (US);
Manoocher Birang, Los Gatos, CA (US);
Alfred Mak, Union City, CA (US);
Simon W Tam, Milpitas, CA (US);
Applied Materials Inc., Santa Clara, CA (US);
Abstract
A method of making a dielectric chuck for securing a semiconductor wafer on a pedestal having multiple apertures for the introduction of cooling gas beneath the wafer. The wafer is held by electrostatic force against a laminate of an electrode layer sandwiched between two dielectric layers in accordance with the method, such that the laminate presents a planar surface to the wafer for a substantial distance beyond the outer edge of the electrode layer. The laminate construction method ensures that a large wafer area beyond the outer edge of the electrode is in contact with the laminate, to minimize cooling gas leakage near the edge, and provides a longer useful life by increasing the path length of dielectric material between the electrode layer and potentially damaging plasma material surrounding the chuck.