The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 1997
Filed:
Dec. 13, 1994
Daniel Fitzpatrick, Santa Clara, CA (US);
Kenneth S Kundert, Belmont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A behavioral description translation method is disclosed wherein output and input access functions are identified from behavioral descriptions of the underlying circuit and its components. Structural representations of the behavioral descriptions of the circuits components as identified by the access functions are constructed therefrom from a set of branch primitives provided. From the constructed branches, those S-type branches, i.e., voltage sources and current probes, that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches are collapsed. Those P-type branches, i.e., the current sources and voltage probes, that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches are collapsed. Then, for every node in the circuit a single relationship that expresses KCL is generated from the collapsed branch relationships. The relationships thus formed are combined to eliminate un-necessary branch relationships to be provided to the circuit simulator. In such a manner, the higher-level behavioral descriptions can be effectively translated into a lower-level specification which describes the circuit to a simulator program.