The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 1997
Filed:
Sep. 26, 1995
Vipul C Patel, San Jose, CA (US);
Kenneth A Poteet, San Jose, CA (US);
Chitranjan N Reddy, Los Altos Hills, CA (US);
Alliance Semiconductor Corporation, San Jose, CA (US);
Abstract
A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).