The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 1997
Filed:
May. 01, 1995
John P Fishburn, Murray Hill, NJ (US);
Craig R Kemp, Topton, PA (US);
Catherine A Schevon, Philadelphia, PA (US);
Todd R Seigfried, Auburn, PA (US);
Sanjiv Taneja, Berkeley Heights, PA (US);
Yu-Chun Wu, Allentown, PA (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
A system and method integrate mask layout tools to automate the generation of mask layouts for fabricating an integrated circuit corresponding to an input netlist and a timing specification. The mask layout is generated by the method including the steps of automatically sizing transistors specified in the netlist, clustering the sized transistors into cells, generating a cell library, and placing-and-routing the cells to generate the mask layout. The system includes associated memory and stored programs, including a plurality of mask layout tools; and a processor operated by an automatic mask layout generation program for sequentially applying the plurality of mask layout tools to generate the mask layout from the input data. The plurality of mask layout tools includes: a transistor sizing tool for sizing transistors and to generate a netlist; a cell library generation tool for generating a cell library from the netlist; a place-and-route tool for generating the mask layout; and optionally a clustering tool for clustering the netlist generated by the transistor sizing tool into a plurality of cells.