The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 1997
Filed:
Sep. 30, 1994
Applicant:
Inventor:
Carl J Simonsen, Aloha, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364490 ; 364488 ; 364489 ; 364491 ; 438129 ; 438599 ;
Abstract
A logic synthesis method uses a two-dimensional sizing progression for selecting gates from a cell library in designing an integrated circuit. The drive load and desired performance for each logic gate in a functional configuration for the integrated circuit may be determined. The device configuration or gate to implement the logic gate may be selected from a cell library. The selected gate has a drive load range encompassing the determined drive load and achieves a desired performance target for the logic gate. A two-dimensional sizing progression may be used to help minimize layout area, power consumption, and performance loss in implementing BiNMOS gates.