The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 1997
Filed:
Dec. 27, 1995
Ming-Hsung Chang, Hsin-Chu, TW;
Jiue-Wen Weng, Chai-Chi, TW;
Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;
Abstract
A method for forming a low voltage coefficient capacitor within an integrated circuit. Formed upon a semiconductor substrate is a first polysilicon layer. Formed directly upon the first polysilicon layer is an Inter Polysilicon Dielectric (IPD) layer. Formed directly upon the Inter Polysilicon Dielectric (IPD) layer is a second polysilicon layer. The first polysilicon layer and the second polysilicon layer each have a resistivity no greater than about 40 ohms per square. Formed directly upon the second polysilicon layer is an amorphous silicon layer. Formed directly upon the amorphous silicon layer is a metal layer which is capable of forming a metal silicide with the amorphous silicon layer. The thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer. Finally, the semiconductor substrate is annealed to form a metal silicide layer from the amorphous silicon layer and the metal layer.