System for loading pll from bus fraction register when bus fraction

Abstract

A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling. The internal and I/O clocks are signaled to stop in response to a NOP micro instruction placed in the pipe line, that indicates that the pipeline is clear of pending instructions. A number of NOPs are executed, the number being determined by the amount of time required by the I/O clock to stop.