The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 1997
Filed:
Jun. 07, 1995
Takashi Iwakiri, Ono, JP;
Kiyomi Hirose, Tsukuba, JP;
Hiroto Shinozuka, Omigawamachi, JP;
Osaomi Enomoto, Ibaraki, JP;
Yasuhiro Okumoto, Ibaraki, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.