Apparatus and method for entry allocation for a buffer resource

Abstract

A two cycle pipelined method and apparatus for allocating a number of vacant entries of a buffer resource and generating a set of enable vectors based thereon for a set of issued instructions. The procedure for determining the vacant entries is spread across two pipestages (clock cycles) of a pipelined superscalar processor. For each pipestage, the system receives information from the previous pipestage as to which entries were eligible for allocation but have not yet received instruction information as well as a set of speculative stall signals. For each pipestage, the reservation station informs the system as to which entries are vacant according to the reservation station's knowledge at that time; this is a preliminary deallocation vector. For each pipestage, the system also receives a list of the instructions for allocation to the reservation station for that cycle. The system formulates a modified deallocation vector from the above information by masking bits of the preliminary deallocation vector and also performs stall checking in the event there are not enough vacant entries. The system interrogates the modified deallocation vector to locate the vacancies within the reservation station for storage of instruction information associated with several issued operations. A general static and dynamic approach are disclosed for performing the vacant entry identification at high speed within a single clock cycle.