The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 1997
Filed:
Jun. 30, 1993
Boubekeur Benhamida, Boise, ID (US);
Grant Richards, Meridian, ID (US);
Stephen H Chan, Sunnyvale, CA (US);
Gyle Yearsley, Boise, ID (US);
Jim Nobugaki, Asao-ku, JP;
Zilog, Inc., Campbell, CA (US);
Abstract
Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.