The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 1997

Filed:

Jul. 30, 1996
Applicant:
Inventors:

Junji Sugisawa, Santa Clara, CA (US);

Dilip Lalwani, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 223 ; 39518306 ;
Abstract

The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.


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