The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 1997
Filed:
Oct. 31, 1994
Shaun Knoll, Portland, OR (US);
Jeff C Morriss, Boulder Creek, CA (US);
Shelagh Callahan, Beaverton, OR (US);
Ajay V Bhatt, El Dorado Hills, CA (US);
Puthiya K Nizar, El Dorado Hills, CA (US);
Richard M Haslam, Hillsboro, OR (US);
Andrew M Volk, Loomis, CA (US);
Sudarshan B Cadambi, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave 'devices', employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.