The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 1997

Filed:

May. 27, 1994
Applicant:
Inventors:

Hiroyuki Yoshida, Ryugasaki, JP;

Takashi Inui, Tshuchiura, JP;

Shigeki Numaga, Ami-machi, JP;

Kiyoshi Nakai, Ohme, JP;

Yukihide Suzuki, Akishima, JP;

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365200 ; 365 63 ; 365 69 ; 365190 ; 36523003 ; 36523006 ;
Abstract

A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.


Find Patent Forward Citations

Yoshida, Hiroyuki. (1997). Semiconductor memory device having plural memory mats with centrally (U.S. Patent No. 5615156). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5615156

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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