The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 1997

Filed:

Sep. 12, 1995
Applicant:
Inventors:

Paul Ta, San Jose, CA (US);

Michael Cheng, San Jose, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03L / ; H04L / ; H04L / ;
U.S. Cl.
CPC ...
331 57 ; 331-2 ; 331173 ; 331185 ; 375372 ; 375376 ;
Abstract

A data retiming system for retiming incoming data and eliminating jitter is described. The data retiming system includes a local clock; a phase aligner for receiving the incoming data and producing a recovered clock from the incoming data, and then producing retimed incoming data by retiming the incoming data with the recovered clock; and a buffer memory for removing jitter from the retimed incoming data by storing the retimed incoming data to the buffer memory in accordance with the recovered clock and reading the stored data from the buffer memory in accordance with the local clock. The data retiming system provides reliable operation even at very high data rates. A freezeable voltage-controlled oscillator for producing a clock signal in accordance with a freeze signal and a frequency control signal is also disclosed. Using current steering techniques, the freezeable voltage-controlled oscillator is able to freeze its output very quickly.


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