Method of delivering stable data across an asynchronous interface

Abstract

The present invention relates to a method and apparatus for asynchronously transferring data from a first synchronous sequential logic circuit which derives its clock source from a first clock to a second synchronous sequential logic circuit which derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided. The invention comprises a data path and a control path; a data synchronizer coupled to the data path for synchronizing data signals; a control synchronizer coupled to the control path for synchronizing control signals; a register coupled in parallel to the data path for storing valid data output from the data synchronizer; a multiplexor having one input coupled to the data path, another input coupled to the register, a selector input coupled to the control path for selecting between receiving as input synchronized data signals or the contents of the register, and an output for transmitting valid data. If metastability is unlikely, the control signal is deasserted causing the multiplexor to select the synchronized data as input. If metastability is likely, the synchronized control signal is asserted causing the multiplexor to select the register as input. The basic test is whether to accept the new state of the data signal or wait and use the old state currently maintained in the register, until such time as the likelihood of metastability has passed, as indicated by the synchronized control signal.