Semiconductor device test circuit having test enable circuitry and test

Abstract

A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device. The test circuit includes a decoder circuit which detects the matching of a first address input corresponding to a test mode, and a latch circuit which latches the signal indicating the matching of the first address input with a test mode. A second decoder circuit then detects the matching of a second address to the test mode, the second address being input when the matching signal for the first address has been latched. A second latch circuit latches the signal indicating the matching of the second address. A third address input is processed by a third decoder circuit and a third latch circuit in the same way. This means that when a plurality of addresses (three addresses in the described example) which are consecutively input to the respective decoder circuits are in a predetermined, specific combination, a test enable signal is output and the test mode is activated.