Address transition detection sensing interface for flash memory having

Abstract

An address transition detection interface is disclosed for a sensing circuit that determines a state of a memory cell having n possible states, where n is greater than 2, and wherein no decoding logic is required to translate outputs of comparators into binary bits. In the case where n is 4, the sensing circuit includes a first reference corresponding to a first threshold voltage level and a first comparator coupled to the memory cell and to the first reference. The first comparator compares a threshold voltage level of the memory cell to the first reference and provides a first result of the comparison as output. The sensing circuit further includes a second reference corresponding to a second threshold voltage level and a third reference corresponding to a third voltage level. A second comparator has one of its inputs coupled to the memory cell and its second input is selectively coupled to either the second reference or the third reference. A selector circuit selects between the second and third references in response to the first result. The selector circuit couples the second reference to the second comparator if the threshold voltage level of the memory cell is less than the first threshold voltage level. The selector circuit couples the third reference to the second comparator if the threshold voltage level of the memory cell is greater than the first voltage level. A forcing circuit provides the first reference to the second comparator in place of the second and third references for a predetermined period following the output of the first result by the first comparator and prior to the selective coupling to the second comparator by the selector circuit of the second reference or the third reference.