The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 1997

Filed:

Feb. 01, 1996
Applicant:
Inventors:

Haruhiko Ueno, Kawasaki, JP;

Shigeru Nagasawa, Kawasaki, JP;

Masayuki Ikeda, Kawasaki, JP;

Naoki Shinjo, Kawasaki, JP;

Ken-ichi Ishizaka, Kawasaki, JP;

Teruo Utsumi, Kawasaki, JP;

Masami Dewa, Kawasaki, JP;

Kazushige Kobayakawa, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39570013 ; 39518319 ; 395852 ; 395873 ;
Abstract

Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.


Find Patent Forward Citations

Loading…