The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 1997
Filed:
Jan. 18, 1995
Kiyoshi Nishimura, Kyoto, JP;
Hideki Hayashi, Kyoto, JP;
Jun Muramoto, Kyoto, JP;
Takaaki Fuchikami, Kyoto, JP;
Hiromi Uenoyama, Kyoto, JP;
Rohm Co., Ltd., , JP;
Abstract
Nonvolatile memory with a simple structure where recorded information can be read without destruction: Voltage is impressed between control gate CG and memory gate MG at a writing operation. A ferroelectric layer 32 is polarized in accordance with the direction of the impressed voltage. The control gate voltage V.sub.CG to make a channel is low when the ferroelectric layer 32 is polarized with the control gate side being positive (polarized with second status). The control gate voltage V.sub.CG to make a channel is high when the ferroelectric layer 32 is polarized with the control gate side being negative (polarized with the first status). The reference voltage V.sub.ref is impressed to the control gate CG at the reading operation. A high drain current flows when the ferroelectric layer is polarized with the second status and low drain current flows when the ferroelectric layer is polarized with the first status. Recorded information can be read by detecting the drain current. With this reading operation, the polarization status is not destroyed.