Solid state imaging device with low trap density

Abstract

A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5') is partially provided on said active layer through a gate insulation layer (4). Said active layer (3') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1). Said active layer (3') is obtained by crystallizing said amorphous silicon layer through a laser anneal process or a high temperature anneal process, and hydrogenation process, and the trap density of said active layer is less than 5.times.10.sup.11 /cm.sup.2. Optical response time is short, less than 500 .mu.sec, so, high speed operation ten times as high as that of a prior image sensor is possible.