The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 1996

Filed:

Jul. 27, 1995
Applicant:
Inventors:

Jay Heeb, Gilbert, AZ (US);

Sunil Shenoy, Portland, OR (US);

Jimmy Wong, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395800 ; 395467 ; 364D / ; 3642318 ; 3642405 ;
Abstract

A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to allow sufficient time for 'hit or miss' detection by a data cache unit. The present invention dynamically expands the instruction pipeline for cacheable LOAD instructions that 'miss' an on-chip data cache when the LOAD is followed by another instruction that uses the bus controller. The dynamic pipeline allows time for the 'hit or miss' detection by the data cache unit without unnecessarily degrading pipeline performance. The present invention offers increased overall microprocessor and computer system performance by allowing efficient implementation of an on-chip data cache. The present invention provides increased performance without undue or overly complex modifications to existing pipeline or data cache circuits.


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