Method for manufacturing a stacked/trench dram capacitor

Abstract

A method for manufacturing a DRAM capacitor on a substrate in which an insulator, a first barrier layer, a first conductive layer and a second barrier layer are sequentially applied over the gate electrode and source/drain areas of the substrate. Portions of the deposited layers above the source/drain areas are removed to form trenches which reach these areas. After portions of the second barrier layer and the first conductive layer are etched away, a conductive material layer is deposited thereover, an n-type dopant is doped into the conductive material layer, the dopant is diffused into the substrate to form n.sup.+ -type diffused regions, and the conductive material layer is shaped to form spaced-apart poly spacers and poly fins. Thereafter the first and the second barrier layers are removed to form a bottom plate of the DRAM capacitor which is defined by the first conductive layer, the poly spacers and the poly fins. Finally, a dielectric film is applied over the bottom plate and a further conductive layer is deposited thereover so that it forms a top plate of the DRAM capacitor. The resulting stack/trench capacitor has a larger dielectric film area and a correspondingly larger capacitance.