The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 1996
Filed:
May. 31, 1995
Gordon W Motley, Ft. Collins, CO (US);
David S Maitland, Ft. Collins, CO (US);
Peter J Meier, Ft. Collins, CO (US);
Hewlett-Packard Co., Palo Alto, CA (US);
Abstract
The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature. Those exhibited variations are communicated by a current mirror to a gate voltage mirror that produces the complementary programming signals, and which themselves constitute negative feedback. The complementary current mirrors are of known of gain, which in conjunction with knowing the value of VDD, allows the determination in advance of a definite table of programming resistance values versus output impedances.