Fabrication process of a semiconductor device with a wiring structure

Abstract

An intermediate insulation layer provided between a wiring of gate electrodes on a semiconductor substrate and a wiring formed in an upper layer includes a first interlayer insulation layer, a silicon rich oxide layer stacked on the first interlayer insulation layer and containing excessive silicon atom, and a second interlayer insulation layer stacked over the silicon rich oxide layer. Processes are provided for selectively performing dry etching for the insulation layers in order to simultaneously and easily form a self-aligned type contact hole on the diffusion layer position at the gap between oppositely arranged gate electrodes and a contact hole on the wiring of the predetermined gate electrode. In this manner, on the diffusion layer and the wiring of the gate electrode, the self-align contact hole and the contact hole are formed in the same process. This permits elimination of the need for margins in formation of the contact hole in the semiconductor device adapted for ultra-high packing density.