The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 1996
Filed:
May. 15, 1995
Takao Akaogi, Kawasaki, JP;
Hiromi Kawashima, Kawasaki, JP;
Tetsuji Takeguchi, Kawasaki, JP;
Ryoji Hagiwara, Kawasaki, JP;
Yasushi Kasa, Kawasaki, JP;
Kiyoshi Itano, Kawasaki, JP;
Yasushige Ogawa, Kasugai, JP;
Shouichi Kawamura, Kawasaki, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.