Memory configuration decoding system having automatic row base address

Abstract

A memory configuration system including a memory controller comprising a set of memory configuration registers which store information related to memory devices installed in random access memory. The memory configuration registers correspond to one or more rows of memory banks in the random access memory. The memory controller also includes a row size and mask generator coupled to the memory configuration register set and a memory configuration decoder coupled to the row size and mask generator. The combination of logic within the row size and mask generator and the memory configuration decoder is used to generate a base address for each row of memory locations within the random access memory. The present invention automatically reconfigures the memory array to define the most populous row as Row 0 regardless of where the largest row is physically populated. This reconfiguration of the memory array is the logical to physical mapping feature provided by the present invention. As an additional feature, the present invention provides a default memory configuration means (i.e. default ordering of rows) for performing the logical to physical mapping in a predictable manner when two or more rows are populated with equal amounts of memory.