The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 1996

Filed:

Mar. 21, 1994
Applicant:
Inventors:

Hartmut Gr utzediek, Mainz, DE;

Joachim Scheerer, Mainz, DE;

Wolfgang Winkler, Frankfurt/Oder, DE;

Michel Pierschel, Berlin, DE;

Karl-Ernst Ehwald, Frankfurt/Oder, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01R / ;
U.S. Cl.
CPC ...
437 31 ; 437 36 ; 437 80 ; 437147 ; 437931 ;
Abstract

A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated ions. This is followed by forming openings in the shielding arrangement by microlithographic processes and anisotropic etching, and then implanting ions via the openings to form one of a base area and a base-connection area of the first conductivity type. Edges of the openings are displaced by isotropic etching of the lower part of the shielding arrangement. Ions are implanted which have been accelerated to energies sufficient to penetrate the one of the base area and base-connection area and a portion of the substrate underlying the one of the base area and base-connection area to form a sub-collector and a graded collector of a second conductivity type for completely encircling and separating a base from the substrate, wherein the sub-collector is more heavily doped than the collector. The base is formed by one of (i) implanting ions between the step of forming openings and the step of implanting ions accelerated, and (ii) implanting ions after the step of implanting ions accelerated. The method further includes forming an emitter, depositing an insulating layer, forming contacts to the base, the emitter and the collector, and forming a metalization arrangement.


Find Patent Forward Citations

Gr utzediek, Hartmut. (1996). Procedure for the manufacture of bipolar transistors without epitaxy and (U.S. Patent No. 5571731). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5571731

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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