The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 1996

Filed:

Sep. 01, 1995
Applicant:
Inventors:

Thomas E Koscica, Clark, NJ (US);

Jian H Zhao, North Brunswick, NJ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257192 ; 257194 ; 257280 ;
Abstract

A heterostructure semiconductor device having source and drain electrodes sistively coupled to opposite ends of a channel, a barrier layer on one side of the channel, a delta doped layer in the channel or within a given distance of it, a gate electrode on the barrier so as to form a Schottky diode and at least one collector electrode mounted on said barrier layer. The collector electrode or electrodes can be resistively coupled to the barrier layer, but preferably the coupling is such as to form a Schottky diode. Changes to the gate bias affect the source current through the field effect mechanism. The collector current depends on the transfer of heated, energized carriers out of the channel over the front heterobarrier. At low gate bias, electrons entering the source travel to the drain while none travel to the collector. Energized carriers are localized to the depletion region due its high electric field drop. At an intermediate gate bias, source current is increased and the voltage drop along the channel shifts more toward the region below the collector. Some heated carriers are then present at the collector's barrier and transfer out of the channel to the collector. At high bias, carrier heating in the channel causes a large fraction of electrons from the source to transfer to the collector. With a rising gate voltage the drain current goes through a smooth peaking and reduction while the collector current rises monotonically.


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