The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 1996

Filed:

May. 01, 1995
Applicant:
Inventors:

Francois Hebert, Sunnyvale, CA (US);

Sze-Hon Kwan, Sunnyvale, CA (US);

Izak Bencuya, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437 40 ;
Abstract

A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.


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