The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 1996

Filed:

Apr. 18, 1995
Applicant:
Inventors:

Andrew Dineen, Derry, NH (US);

George V Ives, Wayland, MA (US);

Assignee:

Draper Laboratory, Inc., Cambridge, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
29841 ; 29836 ; 29847 ;
Abstract

A laminated substrate assembly chip first multichip module and a method of making it includes a plurality of electronic components thinned to a predetermined thickness and mounting them on a fiat substrate in a precise position and orientation; a mechanical spacer layer including a cured film and an adhesive bonded to the flat surface of the substrate surrounding the components; the mechanical spacer layer having a thickness approximately equal to the predetermined thickness of the components and a pattern of holes in it corresponding with the precise position and orientation of the components mounted on the substrate; and a cover layer bonded over the mechanical layer and the tops of the components.


Find Patent Forward Citations

Dineen, Andrew. (1996). Method of fabricating a laminated substrate assembly chips-first (U.S. Patent No. 5564181). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5564181

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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