Method and apparatus for automatically inserting clock buffers into a

Abstract

A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created. The performance is then re-evaluated and, if the minimum threshold still has not been attained, the above process is repeated.