The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 1996

Filed:

Jun. 01, 1995
Applicant:
Inventors:

Keishi Saito, Kyoto-fu, JP;

Tatsuyuki Aoike, Nara, JP;

Masafumi Sano, Nara, JP;

Mitsuyuki Niwa, Nara, JP;

Ryo Hayashi, Nara, JP;

Masahiko Tonogaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437-4 ; 136258 ; 437101 ; 437109 ; 437113 ; 427574 ; 427575 ;
Abstract

A non-monocrystalline silicon semiconductor device having a pin junction is formed by forming a first doped semiconductor layer of a first conductivity disposed on a substrate. A first intrinsic layer is deposited on the first doped semiconductor layer employing RF energy. A second intrinsic layer is deposited on the first intrinsic layer employing microwave energy and RF energy simultaneously. A semiconductor precursor gas, including germanium and a semiconductor precursor gas including silicon are supplied to the second intrinsic layer during its formation. The content of the semiconductor precursor gas containing germanium is greater than the semiconductor gas including silicon in the layer thickness direction in the second intrinsic layer at a P-layer side. A second doped semiconductor layer is deposited on the second intrinsic layer.


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