Dynamic cache coherency method and apparatus using both write-back and

Abstract

A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is 'clean' or 'dirty.' In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU. These two write operations proceed concurrently, and are completed in the same amount of time. When they are completed, the processor cycle is also complete, and the CPU proceeds with its next task. Thereafter, in the background, the posted data in the write buffer is flushed to DRAM, without incurring any CPU overhead.