The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 1996

Filed:

Dec. 20, 1994
Applicant:
Inventors:

Kenichi Kurosawa, Hitachi, JP;

Shigeya Tanaka, Hitachi, JP;

Yasuhiro Nakatsuka, Hitachi, JP;

Tadaaki Bandoh, Ibaraki-ken, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395375 ; 364D / ; 364D / ; 3642287 ; 364229 ; 364230 ; 3642303 ; 3642319 ;
Abstract

A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations. The branch arithmetic unit is controlled by the control unit to effect parallel or consecutive processing of instructions in conjunction with the integer-logic and floating-point arithmetic units.


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