The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 1996

Filed:

Mar. 31, 1993
Applicant:
Inventors:

Shantanu R Gupta, Beaverton, OR (US);

James S Griffith, Aloha, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395800 ; 395375 ; 3642633 ; 364280 ; 3642394 ; 3642318 ; 364261 ; 3642624 ; 364D / ; 364D / ;
Abstract

A method and apparatus for searching for a pattern of values indicating vacancy within a reservation station. The present invention includes a method and apparatus for search a deallocation vector of an instruction scheduler in order to locate, within one clock cycle, a pattern of the first vacancies within the instruction scheduler for storage of instruction information associated with several microprocessor instructions. The present invention advantageously locates four vacant entries of the deallocation vector which specify the first four vacancies within a reservation station of the instruction scheduler and may be utilized to locate the first four vacant entries as well. The present invention performs the above processing utilizing high speed parallel processing methods so that the entire searching, reporting and updating functions, with regard to the deallocation vector, can be completed within one clock cycle. Two embodiments of the present invention, a static and a dynamic embodiment, are presented. Advantageously utilizing the present invention, a multi-instruction processing microprocessor may quickly and efficiently, within one clock cycle, schedule up to four instructions from the instruction decoder to the execution units of the microprocessor.


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