The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 1996
Filed:
Aug. 14, 1995
Michael C Stephens, Jr, San Jose, CA (US);
Chitranjan N Reddy, Los Altos Hills, CA (US);
Kenneth A Poteet, San Jose, CA (US);
Alliance Semiconductor Corporation, San Jose, CA (US);
Abstract
A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.