The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1996
Filed:
Jun. 27, 1995
Rainer Leuschner, Erlangen, DE;
Hellmut Ahne, Roettenbach, DE;
Siegfried Birkle, Hoechstadt, DE;
Albert Hammerschmidt, Erlangen, DE;
Recai Sezi, Roettenbach, DE;
Tobias Noll, Aachen, DE;
Ann Dumoulin, Zedelgem, BE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
A method for manufacturing multichip modules having layer sequences made of dielectric material with conducting tracks embedded therein is characterized by the following features: (1) a temperature-resistant, base-resistant polymer having a dielectric constant .ltoreq.3 is used as a dielectric material, which is applied to a non-conductive substrate and serves as an edge boundary for currentless, autocatalytic build-up of the conducting tracks; (2) the dielectric material is provided with a layer made of material which is soluble in organic solvents (lift-off layer); (3) the dielectric material and the lift-off layer are structured in a single lithographic step, either a direct or an indirect structuring taking place and grooves having an aspect ratio .gtoreq.1 being formed in the dielectric material; (4) a metallic seed layer is applied to the dielectric material or rather to the lift-off layer through vapor deposition in a directed manner; (5) the lift-off layer is removed using an organic solvent; and (6) conducting tracks are created in the grooves through currentless metal deposition.