The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 1996

Filed:

Feb. 18, 1994
Applicant:
Inventors:

Bamdad Bastani, Danville, CA (US);

Larry Wong, Hillsboro, OR (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 47 ; 437191 ; 437918 ;
Abstract

The present invention provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. In accordance with the method, a layer of polysilicon having a first resistance level is formed on a semiconductor circuit structure. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.


Find Patent Forward Citations

Bastani, Bamdad. (1996). Process for fabricating two loads having different resistance levels in (U.S. Patent No. 5554554). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5554554

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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