The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 1996

Filed:

Apr. 01, 1994
Applicant:
Inventors:

Rami Saban, Holon, IL;

Alon Shacham, Tel-Aviv, IL;

Avner Efendovich, Jerusalem, IL;

Varda Karpati, Netanya, IL;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ; H04L / ; H04L / ;
U.S. Cl.
CPC ...
375340 ; 375359 ; 375360 ; 375371 ; 375373 ; 375375 ; 375376 ; 327156 ; 327160 ; 327166 ;
Abstract

The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a 'fast' clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.


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