The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 1996
Filed:
Nov. 05, 1992
Applicant:
Inventors:
Sujit Dey, Plainsboro, NJ (US);
Miodrag Potkonjak, Plainsboro, NJ (US);
Steven Rothweiler, Kunkletown, PA (US);
Assignee:
NEC USA, Inc., Princeton, NJ (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364488 ; 364489 ; 364 / ; 364578 ; 364491 ; 371 221 ; 371 223 ;
Abstract
A technique for optimizing the speed of sequential synchronous digital circuits. First, the bottlenecks that prevent retiming for shortening the delay period are identified and then conditions to eliminate the bottlenecks are derived. This involves identifying the subcircuits associated with the bottlenecks, satisfying a set of timing constraints on the subcircuits, and developing a new circuit that meets the timing constraints. The new circuit free of bottlenecks can generally be retimed by relocation of the forward slack latches to reduce the clock period.