Memory array utilizing multi-state memory cells

Abstract

A non-volatile memory system is disclosed which includes an array of multi-state N channel floating gate memory cells along with associated control circuitry for programming, reading and erasing the cells of the array. Small geometry single transistor memory cells are used which are capable of operating both in the enhancement and the depletion modes of operation. The associated control circuitry includes circuitry for programming selected cells of the array to one of a multiplicity of programmed states, typically four states. At least one of the programmed states results in the cell having a negative threshold voltage, relative to the source region of the cell, thereby indicating depletion mode operation, with the remaining states resulting in the cell having positive threshold voltage. The use of both polarity threshold voltages increases the voltage margin between states thereby enhancing the reliability of read/write operations. The memory read circuitry applies a positive voltage, relative to the source region of the target cell, to the word line associated with the selected cell for carrying out read operations. In addition, the read circuitry applies a negative voltage to the remaining word lines so that deselected cells which are in the same column as the selected cell do not conduct current which would interfere with the reading of the selected cell. This latter feature avoids the necessity of using large geometry split channel memory cells in order to eliminate current flow in deselected cells.