The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1996

Filed:

May. 09, 1995
Applicant:
Inventors:

Koichi Fukuda, Sendai, JP;

Tomofumi Oba, Sendai, JP;

Masanori Miyazaki, Sendai, JP;

Hirofumi Fukui, Daiwa-machi, JP;

Chisato Iwasaki, Sendai, JP;

Yasuhiko Kasama, Sendai, JP;

Tadahiro Ohmi, Aoba-ku, Sandai-shi, Miyagi-ken, JP;

Masaru Kubota, Miyagi-ken, JP;

Hitoshi Kitagawa, Sendai, JP;

Akira Nakano, Furukawa, JP;

Osamu Yoshida, Sendai, JP;

Assignees:

Frontec Incorporated, Sendai, JP;

Other;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; C23C / ;
U.S. Cl.
CPC ...
437241 ; 437 40 ; 437 41 ; 20419223 ;
Abstract

There is provided an electronic device like a TFT using a silicon nitride insulating film of a single layer structure having an excellent dielectric voltage, and a method of producing the electronic device with reliability. In the electronic device, a conductive wiring pattern is deposited on a surface of an electrically insulated substrate, and an insulating layer is formed to cover the wiring pattern and the substrate. The insulating layer is made of a silicon nitride insulating film. A contact angle .theta. between the wiring pattern and the substrate is equals 60.degree. or more, and a value Tn1/Tg of a thickness Tn1 of the silicon nitride insulating film and a thickness Tg of the wiring pattern equals 2 or more. A horizontal distance Tn2 between a rise start position, where the silicon nitride film rises because of a step of the wiring pattern and the top end of the wiring pattern, and Tn1 are in a relation where 0.6.ltoreq.Tn2/Tn1.


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