The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1996

Filed:

Nov. 25, 1994
Applicant:
Inventors:

Majid M Hashemi, Tempe, AZ (US);

Saied N Tehrani, Scottsdale, AZ (US);

Patricia A Norton, Mesa, AZ (US);

Assignee:

Motorola, Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 39 ; 437 41 ; 437192 ; 437912 ; 437944 ; 148D / ; 148D / ; 148D / ; 148D / ; 257283 ; 257486 ;
Abstract

A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN 'T-shaped' Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the 'T-shaped' gate, with source and drain ohmic contacts also self-aligned with respect to the gate.


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Hashemi, Majid. (1996). Method of fabricating self-aligned fet structure having a high (U.S. Patent No. 5550065). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5550065

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