The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 1996
Filed:
Apr. 21, 1994
David L Sprague, Trenton, NJ (US);
Kevin Harney, Brooklyn, NY (US);
Eiichi Kowashi, Lawrenceville, NJ (US);
Michael Keith, Holland, PA (US);
Allen H Simon, Belle Meade, NJ (US);
Gregory M Papadopoulos, Burlinton, MA (US);
Walter P Hays, Brookline, MA (US);
George F Salem, Cambridge, MA (US);
Shih-Wei Shiue, Lexington, MA (US);
Anthony P Bertapelli, Ayer, MA (US);
Vitaly H Shilman, Brookline, MA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.