The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 1996
Filed:
Dec. 22, 1994
William A Brant, Boulder, CO (US);
Gary Neben, Boulder, CO (US);
Michael E Nielson, Broomfield, CO (US);
David C Stallmo, Boulder, CO (US);
EMC Corporation, Hopkinton, MA (US);
Abstract
An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails. A backup power source is provided to ensure that power will be available to at least one of the two memories such that the data that has been received within the controller will always be accessible. Accordingly, since the data will be accessible, even if of a failure of any single component or power source occurs, the controller may acknowledge the write operation requested by the CPU as soon as data is successfully written to both the DATA-RAM and the SHADOW-RAM.