The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 1996

Filed:

Nov. 30, 1994
Applicant:
Inventors:

Yoshiko Yamaguchi, Tokyo, JP;

Yoichi Ohshima, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437 48 ; 437 50 ; 437 52 ;
Abstract

Field oxide films are formed on a semiconductor substrate of first conductivity type to be spaced from each other in the stripe shape. Gate insulating films are formed on the semiconductor substrate between the field oxide films. Word lines or control gate electrodes are formed on the field oxide films and the gate insulating films to be spaced from each other in the stripe shape along a direction perpendicular to the field oxide films. Grooves are formed in the gate insulating films and the field oxide films sandwiched by the word lines. Source regions of second conductivity type are formed in the semiconductor substrate in the grooves formed in the gate insulating films. A common source wiring region of second conductivity type for electrically connecting the respective source regions is formed in the semiconductor substrate in the grooves formed in the field oxide films. The impurity concentration of the common source wiring region is higher than that of the source regions, and the diffusion depth of the common source wiring region is deeper than that of the source regions.


Find Patent Forward Citations

Yamaguchi, Yoshiko. (1996). Method of manufacturing a semiconductor memory device having a common (U.S. Patent No. 5547884). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5547884

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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