The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 1996
Filed:
May. 16, 1995
Stavros Kalafatis, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A digital phase-locked loop having a jitter limited to one-half of a period of the reference clock comprises a generator circuit and a control circuit. The input clock is defined by a plurality of rising edges and falling edges. The generator circuit receives a reference clock and generates the output clock. The phase of the output clock is one of a plurality of selectable phases such that the difference in phases between the output clock and the input clock is limited to one-half of a period of the reference clock once the DPLL locks to the input clock. The control circuit receives the input clock, the reference clock, and the output clock and provides a selection input to the generator circuit to make the phase of the output clock selectable upon each rising edge and upon each falling edge of the input clock.