Non-volatile memory array with over-erase correction

Abstract

A non-volatile memory device is provided having various electrical couplings for maximizing over-erased correction of that device. Over-erased devices within an array can be corrected in bulk, simultaneous with all other devices within the array. Bulk correction of an array of over-erased device is carried forth in a convergence technique which utilizes higher floating gate injection currents. Negatively biased substrate causes an enhancement in the injection current and resulting correction capability of the convergence operation. Moreover, convergence can be carried out with a lesser positive voltage upon the drain region, which implies a reduction in the source-to-drain currents as well as substrate currents during the convergence operation. Accordingly, only over-erased transistors receive sufficient turn-on during convergence, while all other transistors remain off. An array of over-erased and normal transistors undergoing the present convergence operation can be simultaneously corrected with a lessened concern with power consumption.