The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 1996
Filed:
Nov. 04, 1994
Harold W Conru, Essex Junction, VT (US);
Francis E Froebel, Essex Junction, VT (US);
Albert J Gregoritsch, Jr, South Burlington, VT (US);
Sheldon C Rieley, Burlington, VT (US);
Stephen G Starr, Essex Junction, VT (US);
Ronald R Uttecht, Essex Junction, VT (US);
Eric J White, Essex Junction, VT (US);
Jens G Pohl, Bernmardswald-Erlbach, DE;
International Business Machines, Corporation, Armonk, NY (US);
Siemens Aktiengesellschaft, Munich, DE;
Abstract
A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.